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MROD_X_In

I2O_Fifo

Documentation for architecture MROD_X_In/I2O_Fifo/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'I2O_Fifo'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk      : in     std_logic;
   11  --     D_Fifo   : out    std_logic_Vector(31 downto 0);
   12  --     Data     : in     std_logic_Vector(31 downto 0);
   13  --     Empty    : out    std_logic;
   14  --     Full     : out    std_logic;
   15  --     HalfFull : out    std_logic;
   16  --     RdReq    : in     std_logic;
   17  --     Rst_n    : in     std_logic;
   18  --     WrReq    : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of I2O_Fifo is
   23     Component scfifo_512x32
   24        PORT
   25           (
   26              clk          : IN std_logic;
   27              din          : IN std_logic_VECTOR(31 downto 0);
   28              rd_en        : IN std_logic;
   29              rst          : IN std_logic;
   30              wr_en        : IN std_logic;
   31              data_count   : OUT std_logic_VECTOR(8 downto 0);
   32              dout         : OUT std_logic_VECTOR(31 downto 0);
   33              empty        : OUT std_logic;
   34              full         : OUT std_logic
   35           );
   36     End Component;
   37  
   38     Signal RstIntern: Std_Logic;
   39     Signal UsedW: Std_Logic_Vector (8 downto 0);
   40  
   41  begin
   42  
   43     RstIntern <= Not Rst_n;
   44     HalfFull <= UsedW(UsedW'high);
   45  
   46     uc1: scfifo_512x32
   47        Port Map (
   48           clk => Clk,
   49           din => Data,
   50           rd_en => RdReq,
   51           rst => RstIntern,
   52           wr_en => WrReq,
   53           data_count => UsedW,
   54           dout => D_Fifo,
   55           empty => Empty,
   56           full => Full);
   57  
   58  end architecture a0 ; -- of I2O_Fifo
   59