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MROD_X_In

Sharc_Fpga_Mux

Documentation for architecture MROD_X_In/Sharc_Fpga_Mux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Sharc_Fpga_Mux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr          : out    std_logic_Vector(19 downto 0);
   11  --     Data         : out    std_logic_Vector(35 downto 0);
   12  --     FpgaA        : in     std_logic_Vector(17 downto 0);
   13  --     SharcA       : in     std_logic_Vector(21 downto 0);
   14  --     SharcD       : in     std_logic_Vector(31 downto 0);
   15  --     Sharc_Fpga_n : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of Sharc_Fpga_Mux is
   20  
   21  BEGIN
   22     Process (SharcA, SharcD, FpgaA, Sharc_Fpga_n)
   23     -- If FPGA gets access then keep the output databus steady.
   24     -- Otherswise changes on the sharc databus will cause setup and
   25     -- hold violations in the databus pipeline. These violations are
   26     -- not harmfull since the databus is not used while reading the ZBT
   27     -- with the FPGA but it's better to minimize them!
   28     Begin
   29        If Sharc_Fpga_n = '0' Then
   30           Adr(19 Downto 18) <= (Others => '0');
   31           Adr(17 Downto 0) <= FpgaA;
   32           Data(31 Downto 0) <= (Others => '0');
   33           Data(32) <= '1';
   34           Data(33) <= '1';
   35        Else
   36           --Sharc A0 designates use of (D63-D32/RDH_n/WRH_n) or (D31-D0/RDL_n/WRL_n).
   37           --We always use D63-D32 (Odd adresses).
   38           --Reroute Sharc A20-A1 to internal address A19-A0.
   39           --Note that Sharc A21 is in use for Channel A/B selection.
   40           Adr(19 Downto 0) <= SharcA(20 Downto 1);
   41           Data(31 Downto 0) <= SharcD;
   42           Data(32) <= '1';
   43           Data(33) <= '1';
   44        End If;
   45        Data(34) <= '0';
   46        Data(35) <= '0';
   47     End Process;
   48  end architecture a0 ; -- of Sharc_Fpga_Mux
   49