Generated by EASE/HDL for peterj on Mon Jul 02 11:00:53 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'Mux'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- n : positive := 8); 11 -- port( 12 -- A : in std_logic_Vector(n-1 downto 0); 13 -- B : in std_logic_Vector(n-1 downto 0); 14 -- O : out std_logic_Vector(n-1 downto 0); 15 -- SelB_notA : in std_logic); 16 -- 17 -- EASE/HDL end ---------------------------------------------------------------- 18 19 architecture a0 of Mux is 20 21 BEGIN 22 Process (A, B, SelB_notA) 23 Begin 24 If SelB_notA = '1' Then 25 O <= B; 26 Else 27 O <= A; 28 End If; 29 End Process; 30 end architecture a0 ; -- of Mux 31