Generated by EASE/HDL for peterj on Mon Jul 02 11:00:56 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'WordCounter'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- n : positive := 12; 11 -- PresetValue : positive := 2); 12 -- port( 13 -- Clear : in std_logic; 14 -- Clk : in std_logic; 15 -- Inc : in std_logic; 16 -- Q : out std_logic_Vector(n-1 downto 0); 17 -- Rst_n : in std_logic); 18 -- 19 -- EASE/HDL end ---------------------------------------------------------------- 20 21 architecture a0 of WordCounter is 22 23 BEGIN 24 Process (Clk, Rst_n) 25 Variable Cnt: Unsigned(n - 1 Downto 0); 26 Begin 27 If Rst_n = '0' Then 28 Cnt := (Others => '0'); 29 ElsIf Rising_Edge (Clk) Then 30 If Clear = '1' Then 31 Cnt := To_Unsigned(PresetValue,n); 32 ElsIf Inc = '1' Then 33 Cnt := Cnt + 1; 34 End If; 35 End If; 36 Q <= Std_Logic_Vector(Cnt); 37 End Process; 38 end architecture a0 ; -- of WordCounter 39