Generated by EASE/HDL for peterj on Mon Jul 02 11:00:52 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- Architecture 'a0' of 'HoldLowFF. 3 -------------------------------------------------------------------------------- 4 -- Copy of the interface declaration of Entity 'HoldLowFF' : 5 -- 6 -- port( 7 -- Clk : in std_logic; 8 -- D : in std_logic; 9 -- Q : out std_logic; 10 -- Res : in std_logic; 11 -- Rst_n : in std_logic); 12 -- 13 -- EASE/HDL end ---------------------------------------------------------------- 14 15 architecture a0 of HoldLowFF is 16 17 BEGIN 18 Process (Clk, Rst_n) 19 Begin 20 If Rst_n = '0' Then 21 Q <= '0'; 22 ElsIf Clk = '1' And Clk'Event Then 23 If D = '1' then 24 Q <= '1'; 25 ElsIf Res = '1' Then 26 Q <= '0'; 27 End If; 28 End If; 29 End Process; 30 end architecture a0 ; -- of HoldLowFF 31