Generated by EASE/HDL for peterj on Mon Jul 02 11:00:50 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'AllmostFullGen'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- AllmostFull : out std_logic; 11 -- Full : in std_logic; 12 -- UsedW : in std_logic_Vector(8 downto 0)); 13 -- 14 -- EASE/HDL end ---------------------------------------------------------------- 15 16 architecture a0 of AllmostFullGen is 17 Signal UsedW_Intern: Unsigned(9 Downto 0); 18 Constant LeftWords: integer := 7; 19 BEGIN 20 -- Use the Full Flag to distinguish between UsedW = "000000" AND Full = '1' = Fifo-Full 21 -- Or UsedW = "000000" AND Full = '0' is Fifo-Empty. 22 UsedW_Intern(9) <= Full; 23 UsedW_Intern(8 Downto 0) <= Unsigned(UsedW); 24 25 Process (UsedW_Intern) 26 Begin 27 If To_Integer(UsedW_Intern) >= (511 - LeftWords) Then 28 AllmostFull <= '1'; 29 Else 30 AllmostFull <= '0'; 31 End If; 32 End Process; 33 end architecture a0 ; -- of AllmostFullGen 34