Generated by EASE/HDL for peterj on Mon Jul 02 11:00:53 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'MTrailer_Mux'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Din : in std_logic_Vector(31 downto 0); 11 -- Dout : out std_logic_Vector(31 downto 0); 12 -- EVID : in std_logic_Vector(11 downto 0); 13 -- Is_TWC : in std_logic; 14 -- WordCnt : in std_logic_Vector(11 downto 0)); 15 -- 16 -- EASE/HDL end ---------------------------------------------------------------- 17 18 architecture a0 of MTrailer_Mux is 19 20 BEGIN 21 Process (Is_TWC, Din, WordCnt, EVID) 22 Begin 23 If Is_TWC = '1' Then 24 Dout(31 Downto 24) <= Din(31 Downto 24); 25 Dout(23 Downto 12) <= EVID; 26 Dout(11 Downto 0) <= WordCnt; 27 Else 28 Dout <= Din; 29 End If; 30 End Process; 31 end architecture a0 ; -- of MTrailer_Mux 32