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MROD_X_In

ReadyGen

Documentation for architecture MROD_X_In/ReadyGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'ReadyGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     T_Ready        :  time := 750 ns;
   11  --     T_MgtReady     :  time := 400 ns;
   12  --     T_MgtPowerDown :  time := 100 ns);
   13  --   port(
   14  --     Locked        : in     std_logic;
   15  --     MGT_PowerDown : out    std_logic;
   16  --     MGT_Rst       : out    std_logic;
   17  --     Ready         : out    std_logic;
   18  --     Rst_n         : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of ReadyGen is
   23  
   24  begin
   25     Process (Rst_n, Locked)
   26     Begin
   27        If Now = 0 ns Then
   28           Ready <= '0', '1' after T_Ready;
   29           MGT_Rst <= '1', '0' after T_MgtReady;
   30           MGT_PowerDown <= '0';
   31        ElsIf Rst_n = '0' Or Locked = '0' Then
   32           Ready <= '0';
   33           MGT_Rst <= '1';         
   34           MGT_PowerDown <= '0';
   35        ElsIf Rising_Edge(Rst_n) And Locked = '1' Then
   36           Ready <= '0', '1' after T_Ready;
   37           MGT_Rst <= '1', '0' after T_MgtReady;
   38           MGT_PowerDown <= '0';
   39        ElsIf Rising_Edge(Locked) And Rst_n = '1' Then
   40           --Xilinx Answer Record #18849:
   41           --"A reference clock must be available at all times.
   42           --If this is not the case you should toggle the POWERDOWN pin when the reference clock
   43           --does become available to ensure that the PMA is properly initialized."
   44           MGT_PowerDown <= '1', '0' after T_MgtPowerDown;
   45           Ready <= '0', '1' after T_Ready;
   46           MGT_Rst <= '1', '0' after T_MgtReady;
   47        End If;
   48     End Process;
   49  end architecture a0 ; -- of ReadyGen
   50