Generated by EASE/HDL for peterj on Mon Jul 02 11:00:52 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'ID_Replace'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- D : in std_logic_Vector(31 downto 0); 11 -- GOL_Err : in std_logic; 12 -- GOL_ErrCode : in std_logic_Vector(3 downto 0); 13 -- Header : in std_logic; 14 -- Q : out std_logic_Vector(31 downto 0); 15 -- TDC_No : in std_logic_Vector(4 downto 0); 16 -- TDC_ParErr : in std_logic; 17 -- TDC_ParErrCode : in std_logic_Vector(3 downto 0)); 18 -- 19 -- EASE/HDL end ---------------------------------------------------------------- 20 21 architecture a0 of ID_Replace is 22 23 BEGIN 24 Process (D, GOL_Err, GOL_ErrCode, TDC_ParErr, TDC_ParErrCode, Header, TDC_No) 25 Begin 26 --Note the priority: 27 --Highest Priority has the GOL_Error Replacement code 28 --Second TDC_Error Replacement Code 29 --Last the TDC-ID rep[lavement in the TDC-Header 30 31 If GOL_Err = '1' Then 32 Q(31 Downto 28) <= GOL_ErrCode; 33 Q(27 Downto 24) <= D(31 Downto 28); --Bits 27..24 represent the original ID 34 Q(23 Downto 0) <= D(23 Downto 0); 35 ElsIf TDC_ParErr = '1' Then 36 Q(31 Downto 28) <= TDC_ParErrCode; 37 Q(27 Downto 24) <= D(31 Downto 28); --Bits 27..24 represent the original ID 38 Q(23 Downto 0) <= D(23 Downto 0); 39 ElsIf Header = '1' Then 40 Q(31 Downto 29) <= D(31 Downto 29); 41 Q(28 Downto 24) <= TDC_No; 42 Q(23 Downto 0) <= D(23 Downto 0); 43 Else 44 Q <= D; 45 End IF; 46 End Process; 47 end architecture a0 ; -- of ID_Replace 48