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MROD_X_In

ClockDoubler

Documentation for architecture MROD_X_In/ClockDoubler/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'ClockDoubler'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     CSM_50MHz :  boolean := False);
   11  --   port(
   12  --     Clk    : in     std_logic;
   13  --     Locked : out    std_logic;
   14  --     Rst_n  : in     std_logic;
   15  --     x1Clk  : out    std_logic;
   16  --     x2Clk  : out    std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of ClockDoubler is
   21     Component ClockDoubler_MGT_GOL_25Mhz_in
   22         port (
   23            RST_IN : in std_logic;
   24            CLKIN_IN : in std_logic;
   25            LOCKED_OUT : out std_logic;
   26            CLK0_OUT : out std_logic;
   27            CLKIN_IBUFG_OUT : out std_logic;
   28            CLK2X_OUT : out std_logic);
   29     end Component;
   30     Component ClockDoubler_MGT_GOL_50Mhz_in
   31         port (
   32            RST_IN : in std_logic;
   33            CLKIN_IN : in std_logic;
   34            LOCKED_OUT : out std_logic;
   35            CLK0_OUT : out std_logic;
   36            CLKIN_IBUFG_OUT : out std_logic;
   37            CLK2X_OUT : out std_logic);
   38     end Component;
   39     Signal Internal_Reset: std_logic;
   40     Signal Internal_x2Clk: std_logic;
   41  begin
   42     Internal_Reset <= Not Rst_n;
   43  
   44  
   45     Doubler25_In: if CSM_50MHz=FALSE generate
   46     ClockDoubler_MGT25 : ClockDoubler_MGT_GOL_25MHz_in   -- Use Clock doubler with 25 MHz input
   47        Port Map (
   48            RST_IN => Internal_Reset,
   49            CLKIN_IN => Clk,
   50            LOCKED_OUT => Locked,
   51            CLK0_OUT => x1Clk,
   52            CLKIN_IBUFG_OUT => open,
   53            CLK2X_OUT => Internal_x2Clk);
   54     end generate;
   55  
   56     Doubler50_In: if CSM_50MHz=TRUE generate
   57     ClockDoubler_MGT50 : ClockDoubler_MGT_GOL_50MHz_in  -- Use Clock doubler with 50 MHz input
   58        Port Map (
   59            RST_IN => Internal_Reset,
   60            CLKIN_IN => Clk,
   61            LOCKED_OUT => Locked,
   62            CLK0_OUT => x1Clk,
   63            CLKIN_IBUFG_OUT => open,
   64            CLK2X_OUT => Internal_x2Clk);
   65     end generate;
   66     x2Clk <= Not Internal_x2Clk; 
   67  end architecture a0 ; -- of ClockDoubler
   68