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MROD_X_In

FIFO_GOLA

Documentation for architecture MROD_X_In/FIFO_GOLA/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FIFO_GOLA'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk    : in     std_logic;
   11  --     D      : in     std_logic_Vector(31 downto 0);
   12  --     Empty  : out    std_logic;
   13  --     Full   : out    std_logic;
   14  --     Q      : out    std_logic_Vector(31 downto 0);
   15  --     RX_Clk : in     std_logic;
   16  --     RdReq  : in     std_logic;
   17  --     Rst_n  : in     std_logic;
   18  --     WrReq  : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of FIFO_GOLA is
   23     component fifo_gola_32x511
   24        port (
   25           din: IN std_logic_VECTOR(31 downto 0);
   26           wr_en: IN std_logic;
   27           wr_clk: IN std_logic;
   28           rd_en: IN std_logic;
   29           rd_clk: IN std_logic;
   30           ainit: IN std_logic;
   31           dout: OUT std_logic_VECTOR(31 downto 0);
   32           full: OUT std_logic;
   33           empty: OUT std_logic);
   34     end component;
   35     signal InternReset: Std_Logic;
   36  begin
   37  
   38     InternReset <= Not Rst_n;
   39  
   40     U0: fifo_gola_32x511
   41        port map (
   42           din => D,
   43           wr_en => WrReq,
   44           wr_clk => Rx_Clk,
   45           rd_en => RdReq,
   46           rd_clk => Clk,
   47           ainit => InternReset,
   48           dout => Q,
   49           full => Full,
   50           empty => Empty);
   51  end architecture a0 ; -- of FIFO_GOLA
   52