Back

Index

MROD_X_In

CSM_GOLParity

Documentation for architecture MROD_X_In/CSM_GOLParity/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'CSM_GOLParity.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'CSM_GOLParity' :
    5  -- 
    6  --   generic(
    7  --     n :  natural := 26 );
    8  --   port(
    9  --     D             : in     std_logic_Vector(31 downto 0);
   10  --     ForceGOL_Err  : in     std_logic;
   11  --     GOLEven_Odd_n : in     std_logic;
   12  --     Q             : out    std_logic_Vector(31 downto 0));
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of CSM_GOLParity is
   17  
   18  BEGIN
   19  -- The parity bit send with the 31 databits is located in bit 'n' of
   20  -- the incomming data word.
   21  -- Parity is checked over the full 32 bits (thus including bit the parity
   22  -- bit 'n').
   23  -- The parity bit is fed back into bit 'n'.
   24  
   25     Process (D)
   26        Variable Par: Std_Logic;
   27     Begin
   28        -- Set initial value for Par thus setting Even or Odd
   29        Par := Not GOLEven_Odd_n;
   30  
   31        -- Caculate parity over all 32 bits
   32        For k In 0 to 31 Loop
   33           Par := Par XOR D(k);
   34        End Loop;
   35  
   36        -- Parity is to be inserted in bit 'n' so exclude bit(n) again
   37        -- and assign par to this bit;
   38        Par := Par Xor D(n);
   39        Q <= D;
   40  
   41        If ForceGOL_Err = '0' Then
   42           Q(n) <= Par;
   43        Else
   44           Q(n) <= NOT Par;
   45        End If;
   46  
   47     End Process;
   48  end architecture a0 ; -- of CSM_GOLParity
   49