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MROD_X_In

Tri_SepOe

Documentation for architecture MROD_X_In/Tri_SepOe/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Tri_SepOe'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     I    : in     std_logic_Vector(n-1 downto 0);
   13  --     O    : out    std_logic_Vector(n-1 downto 0);
   14  --     Oe_n : in     std_logic_Vector(n-1 downto 0));
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of Tri_SepOe is
   19  
   20  begin
   21     Process (I, Oe_n)
   22     Begin
   23        For j In n-1 Downto 0 Loop
   24           If Oe_n(j) = '0' Then
   25              O(j) <= I(j);
   26           Else
   27              O(j) <= 'Z';
   28           End If;
   29        End Loop;
   30     End Process;
   31  end architecture a0 ; -- of Tri_SepOe
   32