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MROD_X_In

AndGMultiple

Documentation for architecture MROD_X_In/AndGMultiple/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AndGMultiple'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n         :  positive := 32;
   11  --     Implement :  String := "FFFFFFFF");
   12  --   port(
   13  --     A : in     std_logic_Vector(n-1 downto 0);
   14  --     B : in     std_logic_Vector(n-1 downto 0);
   15  --     Q : out    std_logic_Vector(n-1 downto 0));
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of AndGMultiple is
   20  
   21  BEGIN
   22     Q <= (A AND B) And HexToStdLogicVector(Implement,n);
   23  end architecture a0 ; -- of AndGMultiple
   24