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MROD_X_In

RdPulseGen

Documentation for architecture MROD_X_In/RdPulseGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RdPulseGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     MS_Wait :  natural := 1);
   11  --   port(
   12  --     A21_Select : in     std_logic;
   13  --     Adr        : in     std_logic_Vector(21 downto 0);
   14  --     Clk        : in     std_logic;
   15  --     MS_n       : in     std_logic;
   16  --     Rd_n       : in     std_logic;
   17  --     Read       : out    std_logic;
   18  --     Rst_n      : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of RdPulseGen is
   23  
   24  BEGIN
   25     Process (Clk, Rst_n, Rd_n, MS_n, Adr, A21_Select)
   26        Variable WaitCnt : Natural Range 0 To 3;
   27     Begin
   28        If Rst_n = '0' Then
   29           Read <= '0';
   30        ElsIf (Rd_n = '0' And MS_n = '0' And Adr(21) = A21_Select) And WaitCnt = MS_Wait Then
   31           Read <= '1';
   32        Else
   33           Read <= '0';
   34        End If;
   35        
   36        If Rst_n = '0' Then
   37           WaitCnt := 0;
   38        ElsIf Rising_Edge(Clk) Then
   39           If NOT (Rd_n = '0' And MS_n = '0' And Adr(21) = A21_Select) Or (WaitCnt = MS_Wait) Then
   40              WaitCnt := 0;
   41           Else
   42              WaitCnt := WaitCnt + 1;
   43           End If;
   44        End If;
   45     End Process;
   46  end architecture a0 ; -- of RdPulseGen
   47