Generated by EASE/HDL for peterj on Mon Jul 02 11:00:55 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'RdoutEnReg'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- Init : String := "3FFFF"); 11 -- port( 12 -- Clk : in std_logic; 13 -- Data : in std_logic_Vector(31 downto 0); 14 -- Full : in std_logic_Vector(17 downto 0); 15 -- Index : in std_logic_Vector(17 downto 0); 16 -- Ld : in std_logic; 17 -- PartitionFull : out std_logic; 18 -- RdOutEn : out std_logic_Vector(17 downto 0); 19 -- RdOutMax : in std_logic; 20 -- Rst_n : in std_logic); 21 -- 22 -- EASE/HDL end ---------------------------------------------------------------- 23 24 architecture a0 of RdoutEnReg is 25 26 begin 27 Process (Clk, Rst_n) 28 Variable Reg: Std_Logic_Vector(17 Downto 0); 29 Begin 30 If Rst_n = '0' Then 31 --After reset all memory partitions are enabled for readout. 32 Reg := HexToStdLogicVector(Init,18); 33 PartitionFull <= '0'; 34 ElsIf Rising_Edge(Clk) Then 35 PartitionFull <= '0'; 36 For I in 0 to 17 Loop 37 --Disable partition for readout when the partition 38 --is currently enabled and full. 39 --Generate a partition full interrupt. 40 If Full(I) = '1' And Reg(I) = '1' Then 41 Reg(I) := '0'; 42 PartitionFull <= '1'; 43 --Also Disable partition for readout when the partition 44 --is currently enabled and the Maximum allowable readout 45 --count is exceeded (Indexpoints the partition to switch off). 46 ElsIf RdOutMax = '1' And Index(I) = '1' And Reg(I) = '1' Then 47 Reg(I) := '0'; 48 --If Sharc is writing data load the register. 49 ElsIf Ld = '1' Then 50 Reg(I) := Data(I); 51 End If; 52 End Loop; 53 End If; 54 RdOutEn <= Reg; 55 End Process; 56 end architecture a0 ; -- of RdoutEnReg 57