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MROD_X_In

AndInvGMultiple

Documentation for architecture MROD_X_In/AndInvGMultiple/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'AndInvGMultiple.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'AndInvGMultiple' :
    5  -- 
    6  --   generic(
    7  --     n         :  positive := 32 ;
    8  --     Implement :  String := "FFFFFFFF" );
    9  --   port(
   10  --     A  : in     std_logic_Vector(n-1 downto 0);
   11  --     Bn : in     std_logic_Vector(n-1 downto 0);
   12  --     Q  : out    std_logic_Vector(n-1 downto 0));
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of AndInvGMultiple is
   17  
   18  BEGIN
   19     Q <= (A AND (NOT Bn)) And HexToStdLogicVector(Implement,n);
   20  end architecture a0 ; -- of AndInvGMultiple
   21