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MROD_X_In

FullDetect

Documentation for architecture MROD_X_In/FullDetect/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FullDetect'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Precision :  positive := 3);
   11  --   port(
   12  --     Clk          : in     std_logic;
   13  --     Rd0          : in     std_logic_Vector(12 downto 0);
   14  --     Rd1          : in     std_logic_Vector(12 downto 0);
   15  --     Rd10         : in     std_logic_Vector(12 downto 0);
   16  --     Rd11         : in     std_logic_Vector(12 downto 0);
   17  --     Rd12         : in     std_logic_Vector(12 downto 0);
   18  --     Rd13         : in     std_logic_Vector(12 downto 0);
   19  --     Rd14         : in     std_logic_Vector(12 downto 0);
   20  --     Rd15         : in     std_logic_Vector(12 downto 0);
   21  --     Rd16         : in     std_logic_Vector(12 downto 0);
   22  --     Rd17         : in     std_logic_Vector(12 downto 0);
   23  --     Rd2          : in     std_logic_Vector(12 downto 0);
   24  --     Rd3          : in     std_logic_Vector(12 downto 0);
   25  --     Rd4          : in     std_logic_Vector(12 downto 0);
   26  --     Rd5          : in     std_logic_Vector(12 downto 0);
   27  --     Rd6          : in     std_logic_Vector(12 downto 0);
   28  --     Rd7          : in     std_logic_Vector(12 downto 0);
   29  --     Rd8          : in     std_logic_Vector(12 downto 0);
   30  --     Rd9          : in     std_logic_Vector(12 downto 0);
   31  --     Rst_n        : in     std_logic;
   32  --     Wr0          : in     std_logic_Vector(12 downto 0);
   33  --     Wr1          : in     std_logic_Vector(12 downto 0);
   34  --     Wr10         : in     std_logic_Vector(12 downto 0);
   35  --     Wr11         : in     std_logic_Vector(12 downto 0);
   36  --     Wr12         : in     std_logic_Vector(12 downto 0);
   37  --     Wr13         : in     std_logic_Vector(12 downto 0);
   38  --     Wr14         : in     std_logic_Vector(12 downto 0);
   39  --     Wr15         : in     std_logic_Vector(12 downto 0);
   40  --     Wr16         : in     std_logic_Vector(12 downto 0);
   41  --     Wr17         : in     std_logic_Vector(12 downto 0);
   42  --     Wr2          : in     std_logic_Vector(12 downto 0);
   43  --     Wr3          : in     std_logic_Vector(12 downto 0);
   44  --     Wr4          : in     std_logic_Vector(12 downto 0);
   45  --     Wr5          : in     std_logic_Vector(12 downto 0);
   46  --     Wr6          : in     std_logic_Vector(12 downto 0);
   47  --     Wr7          : in     std_logic_Vector(12 downto 0);
   48  --     Wr8          : in     std_logic_Vector(12 downto 0);
   49  --     Wr9          : in     std_logic_Vector(12 downto 0);
   50  --     ZBT_Full     : out    std_logic_Vector(17 downto 0);
   51  --     ZBT_HalfFull : out    std_logic_Vector(17 downto 0));
   52  -- 
   53  -- EASE/HDL end ----------------------------------------------------------------
   54  
   55  architecture a0 of FullDetect is
   56     Constant LowerRange: Natural := 12 - (Precision - 1);
   57  BEGIN
   58     Process (Clk, Rst_n)
   59        Variable Diff: Unsigned(12 downto LowerRange);
   60     Begin
   61        If Rst_n = '0' Then
   62           ZBT_Full <= (Others => '0');
   63           ZBT_HalfFull <= (Others => '0');
   64        ElsIf Rising_Edge(Clk) Then
   65           ZBT_Full <= (Others => '0');
   66           ZBT_HalfFull <= (Others => '0');
   67  
   68  --There is a Full condition when the high order Write pointer bits approach the high order Read pointer
   69  --bits minus 2.
   70  --!!!NOTE THAT MINUS 1 WILL NOT WORK!!!
   71  --Example: Precision = 3 (1 Kword distance)
   72  --WrPtr = 0x03FC (so Wr(12..10) = 0)
   73  --The Read pointer will read till 0x03FB (because this was the last word in the ZBT). But Watch out! To read
   74  --up until address 0x03FB, the read address pointer which is filling the pipeline to the ZBT memory will count
   75  --until address 0x0401 (so Rd(12..10) = 1) which whould make wr(12..10) = Rd(12..10) - 1 TRUE!
   76  --The equation Wr(12..10) = Rd(12..10) - 2 enables the read pointer to read 1 Kwords past the write pointer without
   77  --an error. Note that this situation cannot occur since we will only read until the correct TDC trailer is found
   78  --in the ZBT memory and this trailer is guranteed to be present because of the tetris register output. Note also that
   79  --reading past the write pointer is not a full condition but an empty condition!
   80  
   81  --For the same reason as descirbed above the equation for HalfFull is:
   82  --Wr(12..10) + 1 - Rd(12..10) >= 0
   83  
   84           If Unsigned(Wr0(12 downto LowerRange)) = Unsigned(Rd0(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
   85              ZBT_Full(0) <= '1';
   86           End If;
   87           Diff := Unsigned(Wr0(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd0(12 downto LowerRange));
   88           ZBT_HalfFull(0) <= Diff(12);
   89  
   90           If Unsigned(Wr1(12 downto LowerRange)) = Unsigned(Rd1(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
   91              ZBT_Full(1) <= '1';
   92           End If;
   93           Diff := Unsigned(Wr1(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd1(12 downto LowerRange));
   94           ZBT_HalfFull(1) <= Diff(12);
   95  
   96           If Unsigned(Wr2(12 downto LowerRange)) = Unsigned(Rd2(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
   97              ZBT_Full(2) <= '1';
   98           End If;
   99           Diff := Unsigned(Wr2(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd2(12 downto LowerRange));
  100           ZBT_HalfFull(2) <= Diff(12);
  101  
  102           If Unsigned(Wr3(12 downto LowerRange)) = Unsigned(Rd3(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  103              ZBT_Full(3) <= '1';
  104           End If;
  105           Diff := Unsigned(Wr3(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd3(12 downto LowerRange));
  106           ZBT_HalfFull(3) <= Diff(12);
  107  
  108           If Unsigned(Wr4(12 downto LowerRange)) = Unsigned(Rd4(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  109              ZBT_Full(4) <= '1';
  110           End If;
  111           Diff := Unsigned(Wr4(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd4(12 downto LowerRange));
  112           ZBT_HalfFull(4) <= Diff(12);
  113  
  114           If Unsigned(Wr5(12 downto LowerRange)) = Unsigned(Rd5(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  115              ZBT_Full(5) <= '1';
  116           End If;
  117           Diff := Unsigned(Wr5(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd5(12 downto LowerRange));
  118           ZBT_HalfFull(5) <= Diff(12);
  119  
  120           If Unsigned(Wr6(12 downto LowerRange)) = Unsigned(Rd6(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  121              ZBT_Full(6) <= '1';
  122           End If;
  123           Diff := Unsigned(Wr6(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd6(12 downto LowerRange));
  124           ZBT_HalfFull(6) <= Diff(12);
  125  
  126           If Unsigned(Wr7(12 downto LowerRange)) = Unsigned(Rd7(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  127              ZBT_Full(7) <= '1';
  128           End If;
  129           Diff := Unsigned(Wr7(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd7(12 downto LowerRange));
  130           ZBT_HalfFull(7) <= Diff(12);
  131  
  132           If Unsigned(Wr8(12 downto LowerRange)) = Unsigned(Rd8(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  133              ZBT_Full(8) <= '1';
  134           End If;
  135           Diff := Unsigned(Wr8(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd8(12 downto LowerRange));
  136           ZBT_HalfFull(8) <= Diff(12);
  137  
  138           If Unsigned(Wr9(12 downto LowerRange)) = Unsigned(Rd9(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  139              ZBT_Full(9) <= '1';
  140           End If;
  141           Diff := Unsigned(Wr9(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd9(12 downto LowerRange));
  142           ZBT_HalfFull(9) <= Diff(12);
  143  
  144           If Unsigned(Wr10(12 downto LowerRange)) = Unsigned(Rd10(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  145              ZBT_Full(10) <= '1';
  146           End If;
  147           Diff := Unsigned(Wr10(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd10(12 downto LowerRange));
  148           ZBT_HalfFull(10) <= Diff(12);
  149  
  150           If Unsigned(Wr11(12 downto LowerRange)) = Unsigned(Rd11(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  151              ZBT_Full(11) <= '1';
  152           End If;
  153           Diff := Unsigned(Wr11(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd11(12 downto LowerRange));
  154           ZBT_HalfFull(11) <= Diff(12);
  155  
  156           If Unsigned(Wr12(12 downto LowerRange)) = Unsigned(Rd12(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  157              ZBT_Full(12) <= '1';
  158           End If;
  159           Diff := Unsigned(Wr12(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd12(12 downto LowerRange));
  160           ZBT_HalfFull(12) <= Diff(12);
  161  
  162           If Unsigned(Wr13(12 downto LowerRange)) = Unsigned(Rd13(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  163              ZBT_Full(13) <= '1';
  164           End If;
  165           Diff := Unsigned(Wr13(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd13(12 downto LowerRange));
  166           ZBT_HalfFull(13) <= Diff(12);
  167  
  168           If Unsigned(Wr14(12 downto LowerRange)) = Unsigned(Rd14(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  169              ZBT_Full(14) <= '1';
  170           End If;
  171           Diff := Unsigned(Wr14(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd14(12 downto LowerRange));
  172           ZBT_HalfFull(14) <= Diff(12);
  173  
  174           If Unsigned(Wr15(12 downto LowerRange)) = Unsigned(Rd15(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  175              ZBT_Full(15) <= '1';
  176           End If;
  177           Diff := Unsigned(Wr15(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd15(12 downto LowerRange));
  178           ZBT_HalfFull(15) <= Diff(12);
  179  
  180           If Unsigned(Wr16(12 downto LowerRange)) = Unsigned(Rd16(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  181              ZBT_Full(16) <= '1';
  182           End If;
  183           Diff := Unsigned(Wr16(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd16(12 downto LowerRange));
  184           ZBT_HalfFull(16) <= Diff(12);
  185  
  186           If Unsigned(Wr17(12 downto LowerRange)) = Unsigned(Rd17(12 downto LowerRange)) - To_Unsigned(2,Precision) Then
  187              ZBT_Full(17) <= '1';
  188           End If;
  189           Diff := Unsigned(Wr17(12 downto LowerRange)) + To_Unsigned(1,Precision) - Unsigned(Rd17(12 downto LowerRange));
  190           ZBT_HalfFull(17) <= Diff(12);
  191        End If;
  192     End Process;
  193  end architecture a0 ; -- of FullDetect
  194