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MROD_X_In

FPGA

Documentation for architecture MROD_X_In/FPGA/Structure

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'Structure' of entity 'FPGA'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     TDC_Num     :  positive := 18;
   11  --     TDC_NumBits :  positive := 5;
   12  --     EVID_Width  :  positive := 12;
   13  --     MS1_Wait    :  natural := 1;
   14  --     Date_ID     :  integer := 0;
   15  --     Revision_ID :  integer := 0);
   16  --   port(
   17  --     A21_Select     : in     std_logic;
   18  --     Adr            : in     std_logic_Vector(21 downto 0);
   19  --     BufA           : out    std_logic_Vector(19 downto 0);
   20  --     BufCE_n        : out    std_logic;
   21  --     BufD           : inout  std_logic_Vector(35 downto 0);
   22  --     BufR_W_n       : out    std_logic;
   23  --     ChaBusy        : out    std_logic;
   24  --     ChaID          : in     std_logic_Vector(2 downto 0);
   25  --     Clk            : in     std_logic;
   26  --     Clkx2          : in     std_logic;
   27  --     DMAR_n         : out    std_logic;
   28  --     Data           : inout  std_logic_Vector(31 downto 0);
   29  --     Empty          : out    std_logic;
   30  --     ErrLED         : out    std_logic;
   31  --     GOL_MOD_DEF0   : in     std_logic;
   32  --     GOL_MOD_DEF1   : in     std_logic;
   33  --     GOL_MOD_DEF2   : in     std_logic;
   34  --     GOL_RATE_SEL   : out    std_logic;
   35  --     GOL_RXN        : in     std_logic;
   36  --     GOL_RXP        : in     std_logic;
   37  --     GOL_RX_LOS     : in     std_logic;
   38  --     GOL_TXN        : out    std_logic;
   39  --     GOL_TXP        : out    std_logic;
   40  --     GOL_TX_Disable : out    std_logic;
   41  --     GOL_TX_Fault   : in     std_logic;
   42  --     GOL_XClk       : in     std_logic;
   43  --     IRQ0_n         : out    std_logic;
   44  --     IRQ1_n         : out    std_logic;
   45  --     IRQ2_n         : out    std_logic;
   46  --     LEDs           : out    std_logic_Vector(3 downto 0);
   47  --     LHC_Clk        : in     std_logic;
   48  --     MS0_n          : in     std_logic;
   49  --     MS1_n          : in     std_logic;
   50  --     MS2_n          : in     std_logic;
   51  --     MS3_n          : in     std_logic;
   52  --     Rocket_RXN     : in     std_logic;
   53  --     Rocket_RXP     : in     std_logic;
   54  --     Rocket_TXN     : out    std_logic;
   55  --     Rocket_TXP     : out    std_logic;
   56  --     Rocket_XClk    : in     std_logic;
   57  --     Rst_n          : in     std_logic;
   58  --     SDRAM_A        : out    std_logic_Vector(12 downto 0);
   59  --     SDRAM_BA       : out    std_logic_Vector(1 downto 0);
   60  --     SDRAM_CAS_n    : out    std_logic;
   61  --     SDRAM_CKE      : out    std_logic;
   62  --     SDRAM_CLK      : out    std_logic;
   63  --     SDRAM_CLKin    : in     std_logic;
   64  --     SDRAM_CS_n     : out    std_logic;
   65  --     SDRAM_DQ       : inout  std_logic_Vector(31 downto 0);
   66  --     SDRAM_DQM      : out    std_logic_Vector(3 downto 0);
   67  --     SDRAM_RAS_n    : out    std_logic;
   68  --     SDRAM_WE_n     : out    std_logic;
   69  --     SMBClk         : out    std_logic;
   70  --     SMBData        : inout  std_logic;
   71  --     SharcRd_n      : in     std_logic;
   72  --     SharcWr_n      : in     std_logic;
   73  --     Spare          : out    std_logic_Vector(4 downto 0);
   74  --     TTC_n          : in     std_logic_Vector(7 downto 0);
   75  --     T_Alert_n      : in     std_logic;
   76  --     TestCon        : out    std_logic_Vector(15 downto 0);
   77  --     UpLED          : out    std_logic);
   78  -- 
   79  -- EASE/HDL end ----------------------------------------------------------------
   80  
   81  architecture Structure of FPGA is
   82  
   83  begin
   84  
   85  end architecture Structure ; -- of FPGA
   86  
   87