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MROD_X_In

DCM_50_100Mhz_Container

Documentation for architecture MROD_X_In/DCM_50_100Mhz_Container/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'DCM_50_100Mhz_Container.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'DCM_50_100Mhz_Container' :
    5  -- 
    6  --   port(
    7  --     Clk100 : out    std_logic;
    8  --     ClkIn  : in     std_logic;
    9  --     Locked : out    std_logic;
   10  --     Rst_n  : in     std_logic);
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of DCM_50_100Mhz_Container is
   15     Component DCM_50_100Mhz is
   16        port (
   17           RST_IN : in std_logic;
   18           CLKIN_IN : in std_logic;
   19           LOCKED_OUT : out std_logic;
   20           CLKFX_OUT : out std_logic;
   21           CLKIN_IBUFG_OUT : out std_logic;
   22           CLK0_OUT : out std_logic);
   23     end Component;
   24  
   25     Signal InternalReset: Std_Logic;
   26  
   27  begin
   28  
   29     InternalReset <= Not Rst_n;
   30                  
   31     U0:DCM_50_100Mhz
   32        port map (
   33           RST_IN => InternalReset,
   34           CLKIN_IN => ClkIn,
   35           LOCKED_OUT => Locked,
   36           CLKFX_OUT => Clk100,
   37           CLKIN_IBUFG_OUT => Open,
   38           CLK0_OUT => Open);
   39                   
   40  end architecture a0 ; -- of DCM_50_100Mhz_Container
   41  
   42