Generated by EASE/HDL for peterj on Mon Jul 02 11:00:53 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'LimitPrlCnt'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Clk : in std_logic; 11 -- Dec : in std_logic; 12 -- Prl : in std_logic; 13 -- PrlVal : in std_logic_Vector(11 downto 0); 14 -- Rst_n : in std_logic; 15 -- TDC_Limit : out std_logic); 16 -- 17 -- EASE/HDL end ---------------------------------------------------------------- 18 19 architecture a0 of LimitPrlCnt is 20 21 begin 22 Process (Clk, Rst_n) 23 Variable Cnt: Unsigned(11 downto 0); 24 Begin 25 If Rst_n = '0' Then 26 Cnt := (Others => '0'); 27 TDC_Limit <= '0'; 28 Elsif Rising_Edge(Clk) Then 29 If Prl = '1' Then 30 Cnt := Unsigned(PrlVal); 31 TDC_Limit <= '0'; 32 ElsIf Dec = '1' And Cnt > 0 Then 33 Cnt := Cnt -1; 34 TDC_Limit <= '0'; 35 ElsIf Cnt = 0 Then 36 TDC_Limit <= '1'; 37 End If; 38 End If; 39 End Process; 40 end architecture a0 ; -- of LimitPrlCnt 41 42