Generated by EASE/HDL for peterj on Mon Jul 02 11:00:56 2007

Documentation for architecture MROD_X_In/TstDetect/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'TstDetect.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'TstDetect' :
    5  -- 
    6  --   port(
    7  --     Clk      : in     std_logic;
    8  --     HalfFull : out    std_logic;
    9  --     Rd0      : in     std_logic_Vector(3 downto 0);
   10  --     Rst_n    : in     std_logic;
   11  --     Wr0      : in     std_logic_Vector(3 downto 0));
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of TstDetect is
   16  BEGIN
   17     Process (Clk, Rst_n)
   18        Variable Diff: Unsigned(3 downto 0);
   19     Begin
   20        If Rst_n = '0' Then
   21           HalfFull <= '0';
   22        ElsIf Rising_Edge(Clk) Then
   23           HalfFull <= '0';
   24  
   25  --There is a Full condition when the high order Write pointer bits approach the high order Read pointer
   26  --bits minus 2.
   27  --!!!NOTE THAT MINUS 1 WILL NOT WORK!!!
   28  --Example: Precision = 3 (1 Kword distance)
   29  --WrPtr = 0x03FC (so Wr(12..10) = 0)
   30  --The Read pointer will read till 0x03FB (because this was the last word in the ZBT). But Watch out! To read
   31  --up until address 0x03FB, the read address pointer which is filling the pipeline to the ZBT memory will count
   32  --until address 0x0401 (so Rd(12..10) = 1) which whould make wr(12..10) = Rd(12..10) - 1 TRUE!
   33  --The equation Wr(12..10) = Rd(12..10) - 2 enables the read pointer to read 1 Kwords past the write pointer without
   34  --an error. Note that this situation cannot occur since we will only read until the correct TDC trailer is found
   35  --in the ZBT memory and this trailer is guranteed to be present because of the tetris register output. Note also that
   36  --reading past the write pointer is not a full condition but an empty condition!
   37  
   38  --For the same reason as descirbed above the equation for HalfFull is:
   39  --Wr(12..10) + 1 - Rd(12..10) >= 0
   40  
   41           Diff := Unsigned(Wr0(3 downto 0)) + To_Unsigned(1,4) - Unsigned(Rd0(3 downto 0));
   42  --         Diff := Unsigned(Wr0(3 downto 0)) - Unsigned(Rd0(3 downto 0));
   43           HalfFull <= Diff(3);
   44  
   45        End If;
   46     End Process;
   47  end architecture a0 ; -- of TstDetect
   48