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MROD_X_In

ClockGen

Documentation for architecture MROD_X_In/ClockGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'ClockGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     GOL_XClk : in     std_logic;
   11  --     Sel50MHz : in     std_logic;
   12  --     XClk     : out    std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of ClockGen is
   17     component Wrapped_IBUFG
   18       port(
   19         O  : out std_ulogic;
   20         I  : in  std_ulogic
   21         );
   22     end component;
   23  
   24     component Wrapped_BUFG
   25       port(
   26         O  : out std_ulogic;
   27         I  : in  std_ulogic
   28         );
   29     end component;
   30  
   31     component Wrapped_BUFGMUX
   32       port(
   33         O   : out std_ulogic;
   34         I0  : in  std_ulogic;
   35         I1  : in  std_ulogic;
   36         S   : in  std_ulogic
   37         );
   38     end component;
   39  
   40     component Wrapped_FD Is
   41       port(
   42         Q  : out std_ulogic;
   43         C : in  std_ulogic;
   44         D : in  std_ulogic
   45         );
   46     end component;
   47  
   48  -- Residu from earlier days...
   49  --   Component DCM_50_100MHz is
   50  --    port (
   51  --        RST_IN : in std_logic;
   52  --        CLKIN_IN : in std_logic;
   53  --        LOCKED_OUT : out std_logic;
   54  --        CLKFX_OUT : out std_logic;
   55  --        CLKIN_IBUFG_OUT : out std_logic;
   56  --        CLK0_OUT : out std_logic);
   57  --   end Component;
   58  
   59     signal GOL_XClk_IBUFG: std_logic;
   60     signal GOL_XClk_Divide2: std_logic;
   61     signal GOL_XClk_Divide2_Inverted: std_logic;
   62  
   63  begin
   64  
   65  -- COL_XClk is a 100 Mhz Crystal Oscillator
   66  -- Either directly couple XClk to Golbal Bufferd GOL_XClk (Case CSM GOL = 50 MHz)
   67  -- OR
   68  -- Divide GOL_XClk by 2 using a toggle Flip-Flop that feed XClk via a Global Buffer (Case CSM GOL = 25 MHz)
   69  
   70  ----------------------------
   71  -- CSM GOL running at 50 MHz
   72  ----------------------------
   73  --   CSM_GOL_50MHz: if CSM_50MHz=TRUE generate
   74  --      X_IBUFG : Wrapped_IBUFG -- Just feed forward 100 Mhz Xtal
   75  --         Port Map (
   76  --            O => XClk,
   77  --            I => GOL_XClk);
   78  --   end generate;
   79  
   80  ----------------------------
   81  -- CSM GOL running at 25 MHz
   82  ----------------------------
   83  --   CSM_GOL_25MHz: if CSM_50MHz=FALSE generate
   84        X_FD : Wrapped_FD     -- Toggle Flip-Flop
   85           Port Map (
   86              Q => GOL_XClk_Divide2,
   87              C => GOL_XClk_IBUFG,
   88              D => GOL_XClk_Divide2_Inverted);
   89  
   90        GOL_XClk_Divide2_Inverted <= Not GOL_XClk_Divide2;
   91  
   92        X_IBUFG : Wrapped_IBUFG   -- Feed the output of the Toggle Flip-Flop to a Golbal Buffer
   93           Port Map (
   94              O => GOL_XClk_IBUFG,
   95              I => GOL_XClk);
   96  
   97        X_BUFGMUX : Wrapped_BUFGMUX   -- Feed the output of the Toggle Flip-Flop to a Golbal Buffer
   98           Port Map (
   99              O => XClk,
  100              I0 => GOL_XClk_Divide2,
  101              I1 => GOL_XClk_IBUFG,
  102              S => Sel50MHz);
  103  --   end generate;
  104  
  105  -- Residu from earlier days...
  106  --   Use_GOLA_LSC: if GolaLSC_100MHz=TRUE generate
  107  --   DCM_50_100 : DCM_50_100MHz -- Use DCM to boost from 50 MHZ xtal to 100 MHz
  108  --      -- Note that the DCM RST_IN is always inactive.
  109  --      -- Do NOT connect the RST_IN signal to the global Rst_n.
  110  --      -- This would cause the DCM to aquire lock while the system
  111  --      -- is already out of reset and functioning.
  112  --      Port Map (
  113  --          RST_IN => '0',
  114  --          CLKIN_IN => GOL_XClk,
  115  --          LOCKED_OUT => Open,
  116  --          CLKFX_OUT => XClk,
  117  --          CLKIN_IBUFG_OUT => Open,
  118  --          CLK0_OUT => Open);
  119  --   end generate;
  120  
  121  end architecture a0 ; -- of ClockGen
  122  
  123