Generated by EASE/HDL for peterj on Mon Jul 02 11:00:50 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'AddValue'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- n : positive := 12; 11 -- Value : natural := 2); 12 -- port( 13 -- I : in std_logic_Vector(n-1 downto 0); 14 -- O : out std_logic_Vector(n-1 downto 0)); 15 -- 16 -- EASE/HDL end ---------------------------------------------------------------- 17 18 architecture a0 of AddValue is 19 20 begin 21 O <= Std_Logic_Vector(Unsigned(I) + To_Unsigned(Value,n)); 22 end architecture a0 ; -- of AddValue 23 24