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MROD_X_In

FullFlagMux

Documentation for architecture MROD_X_In/FullFlagMux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FullFlagMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     LengthFull      : in     std_logic;
   11  --     OutpAllmostFull : in     std_logic;
   12  --     OutpFull        : out    std_logic;
   13  --     Reg1BBit4       : in     std_logic;
   14  --     Reg1BBit5       : in     std_logic;
   15  --     RocketFull      : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of FullFlagMux is
   20  
   21  begin
   22     Process(Reg1BBit4, Reg1BBit5, OutpAllmostFull, LengthFull, RocketFull)
   23     Begin
   24        -- Bit 4
   25        --  0: Legacy MROD-1 mode
   26        --  1: MROD-X Mode
   27        If Reg1BBit4 = '0' Then
   28           -- Legacy MROD-1 mode
   29           OutpFull <= OutpAllmostFull Or LengthFull;
   30        Else
   31           -- Bit 5
   32           --  0: MROD-X Mode
   33           --  1: MROD-X Debug Mode
   34           If Reg1BBit5 = '0' Then
   35              -- Enable Event Builder via Rocket-IO
   36              OutpFull <= RocketFull;
   37           Else
   38              -- Enable Event Builder via Rocket-IO in Debug Mode
   39              OutpFull <= RocketFull Or OutpAllmostFull Or LengthFull;
   40           End If;
   41        End If;
   42     End Process;
   43  end architecture a0 ; -- of FullFlagMux
   44  
   45