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MROD_X_In

PrlCnt

Documentation for architecture MROD_X_In/PrlCnt/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'PrlCnt'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk    : in     std_logic;
   11  --     Dec    : in     std_logic;
   12  --     En     : in     std_logic;
   13  --     PrlVal : in     std_logic_Vector(15 downto 0);
   14  --     Rst_n  : in     std_logic;
   15  --     Spy_n  : out    std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of PrlCnt is
   20  
   21  begin
   22     Process (Clk, Rst_n)
   23        Variable Cnt: Unsigned(15 downto 0);
   24     Begin       
   25        If Rst_n = '0' Then
   26           Cnt := (Others => '0');
   27           Spy_n <= '1';
   28        Elsif Rising_Edge(Clk) Then
   29           If Dec = '1' Then
   30              If Cnt = 0 Then
   31                 Cnt := Unsigned(PrlVal);
   32                 If En = '1' Then
   33                    Spy_n <= '0';
   34                 Else
   35                    Spy_n <= '1';
   36                 End If;
   37              Else
   38                 Cnt := Cnt -1;
   39                 Spy_n <= '1';
   40              End If;
   41           End If;
   42        End If;
   43     End Process;
   44  end architecture a0 ; -- of PrlCnt
   45  
   46