Generated by EASE/HDL for peterj on Mon Jul 02 11:00:54 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'OrG5'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- A : in std_logic; 11 -- B : in std_logic; 12 -- C : in std_logic; 13 -- D : in std_logic; 14 -- E : in std_logic; 15 -- O : out std_logic); 16 -- 17 -- EASE/HDL end ---------------------------------------------------------------- 18 19 architecture a0 of OrG5 is 20 21 BEGIN 22 O <= A Or B Or C Or D Or E; 23 end architecture a0 ; -- of OrG5 24