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MROD_X_In

RstGen

Documentation for architecture MROD_X_In/RstGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RstGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk        : in     std_logic;
   11  --     Config_Rst : out    std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of RstGen is
   16  
   17     Component Wrapped_FDS Is
   18        Port(
   19           Q  : out std_ulogic;
   20           C : in  std_ulogic;
   21           D : in  std_ulogic;
   22           S : in  std_ulogic
   23        );
   24     End Component;
   25  
   26     Component Wrapped_FD Is
   27        Port(
   28           Q  : out std_ulogic;
   29           C : in  std_ulogic;
   30           D : in  std_ulogic
   31        );
   32     End Component;
   33  
   34     Signal out1: std_logic;
   35     Signal out2: std_logic;
   36     Signal out3: std_logic;
   37     Signal out4: std_logic;
   38  
   39     -- Percision Synthesis optimized away the first FF because it has the 'D' input connected to GND.
   40     -- The optimization results in TxRst connected to GlobalGnd.
   41     -- Thus set a NOOPt attribute for the first Flip-Flop
   42     attribute NOOPT: boolean;
   43     attribute NOOPT of Wrapped_FDS: component is TRUE;
   44  
   45  begin
   46  
   47     flop1: Wrapped_FDS port map (D => '0', C => clk, Q => out1, S => '0'); 
   48     flop2: Wrapped_FD port map (D => out1, C => clk, Q => out2); 
   49     flop3: Wrapped_FD port map (D => out2, C => clk, Q => out3); 
   50     flop4: Wrapped_FD port map (D => out3, C => clk, Q => out4); 
   51  
   52     Config_Rst <= out2 or out3 or out4; 
   53  
   54  end architecture a0 ; -- of RstGen
   55  
   56