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MROD_X_In

GOL_Rx_Decode

Documentation for architecture MROD_X_In/GOL_Rx_Decode/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'GOL_Rx_Decode.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'GOL_Rx_Decode' :
    5  -- 
    6  --   port(
    7  --     Clk         : in     std_logic;
    8  --     RXData      : in     std_logic_Vector(15 downto 0);
    9  --     Rst_n       : in     std_logic;
   10  --     RxCharIsK   : in     std_logic_Vector(1 downto 0);
   11  --     RxD         : out    std_logic_Vector(15 downto 0);
   12  --     RxInSync    : in     std_logic;
   13  --     RxIsCarExt  : out    std_logic;
   14  --     RxIsErrProp : out    std_logic;
   15  --     RxIsValid   : out    std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of GOL_Rx_Decode is
   20     --GOL IDLE1 = <K28.5>,<D5.6>
   21     Constant IDLE1_Data: Std_Logic_Vector (15 downto 0) := x"BCC5";
   22     --GOL IDLE2 = <K28.5>,<D16.2>
   23     Constant IDLE2_Data: Std_Logic_Vector (15 downto 0) := x"BC50";
   24     Constant IDLE_K: Std_Logic_Vector (1 downto 0) := "10";
   25     --GOL Carrier Extend = <K23.7>,<K23.7>
   26     Constant CarExt_Data: Std_Logic_Vector (15 downto 0) := x"F7F7";
   27     Constant CarExt_K: Std_Logic_Vector (1 downto 0) := "11";
   28     --GOL Error Propagation = <K30.7>,<K30.7>
   29     Constant ErrProp_K: Std_Logic_Vector (1 downto 0) := "11";
   30     Constant ErrProp_Data: Std_Logic_Vector (15 downto 0) := x"FEFE";
   31    
   32  begin
   33     Process (Clk, Rst_n)
   34     Begin
   35        If Rst_n = '0' Then
   36           RxIsValid <= '0';
   37           RxIsCarExt <= '0';
   38           RxIsErrProp <= '0';
   39           RxD <= (Others => '0');
   40        ElsIf Rising_Edge(Clk) Then
   41           If RxInSync = '1' Then
   42              If (RxData = CarExt_Data) And (RXCharIsK = CarExt_K) Then
   43                 RxIsValid <= '1';
   44                 RxIsCarExt <= '1';
   45                 RxIsErrProp <= '0';
   46                 RxD <= RxData;
   47              Elsif (RxData = ErrProp_Data) And (RXCharIsK = ErrProp_K) Then
   48                 RxIsValid <= '1';
   49                 RxIsCarExt <= '0';
   50                 RxIsErrProp <= '1';
   51                 RxD <= RxData;
   52              ElsIf (RXCharIsK /= IDLE_K) Then
   53                 RxIsValid <= '1';
   54                 RxIsCarExt <= '0';
   55                 RxIsErrProp <= '0';
   56                 --The GOL sends its data in the following order
   57                 --din<7:0>, din<15:8>, din<23:16>, din<31:24>
   58                 --The Xilinx MGT receives this data as two 16-bit words
   59                 --RxData<15:0> = din<7:0>, din<15:8>
   60                 --RxData<15:0> = din<23:16>, din<31:24>
   61                 --This means a byte order remap must be done.
   62                 RxD (15 downto 8) <= RxData(7 Downto 0);
   63                 RxD (7 downto 0) <= RxData(15 Downto 8);
   64              Else
   65                 RxIsValid <= '0';
   66                 RxIsCarExt <= '0';
   67                 RxIsErrProp <= '0';
   68                 -- RxD <= RxData;        May keep its last value
   69              End If;            
   70           Else
   71              RxIsValid <= '0';
   72              RxIsCarExt <= '0';
   73              RxIsErrProp <= '0';
   74              -- RxD <= (Others => '0');  May keep its last value
   75           End If;
   76        End If;   
   77     End Process;
   78  end architecture a0 ; -- of GOL_Rx_Decode
   79  
   80