Documentation for architecture MROD_X_In/GOL_Rx_Decode/a0
VHDL Contents
1 architecture a0 of GOL_Rx_Decode is
20 Constant IDLE1_Data: Std_Logic_Vector (15 downto 0) := x"BCC5";
22 Constant IDLE2_Data: Std_Logic_Vector (15 downto 0) := x"BC50";
24 Constant IDLE_K: Std_Logic_Vector (1 downto 0) := "10";
25 Constant CarExt_Data: Std_Logic_Vector (15 downto 0) := x"F7F7";
27 Constant CarExt_K: Std_Logic_Vector (1 downto 0) := "11";
28 Constant ErrProp_K: Std_Logic_Vector (1 downto 0) := "11";
30 Constant ErrProp_Data: Std_Logic_Vector (15 downto 0) := x"FEFE";
31
32 begin
33 Process (Clk, Rst_n)
34 Begin
35 If Rst_n = '0' Then
36 RxIsValid <= '0';
37 RxIsCarExt <= '0';
38 RxIsErrProp <= '0';
39 RxD <= (Others => '0');
40 ElsIf Rising_Edge(Clk) Then
41 If RxInSync = '1' Then
42 If (RxData = CarExt_Data) And (RXCharIsK = CarExt_K) Then
43 RxIsValid <= '1';
44 RxIsCarExt <= '1';
45 RxIsErrProp <= '0';
46 RxD <= RxData;
47 Elsif (RxData = ErrProp_Data) And (RXCharIsK = ErrProp_K) Then
48 RxIsValid <= '1';
49 RxIsCarExt <= '0';
50 RxIsErrProp <= '1';
51 RxD <= RxData;
52 ElsIf (RXCharIsK /= IDLE_K) Then
53 RxIsValid <= '1';
54 RxIsCarExt <= '0';
55 RxIsErrProp <= '0';
56 RxD (15 downto 8) <= RxData(7 Downto 0);
63 RxD (7 downto 0) <= RxData(15 Downto 8);
64 Else
65 RxIsValid <= '0';
66 RxIsCarExt <= '0';
67 RxIsErrProp <= '0';
68 End If;
70 Else
71 RxIsValid <= '0';
72 RxIsCarExt <= '0';
73 RxIsErrProp <= '0';
74 End If;
76 End If;
77 End Process;
78 end architecture a0 ;