Generated by EASE/HDL for peterj on Mon Jul 02 11:00:51 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'Fiber'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- CSM_RXN : in std_logic; 11 -- CSM_RXP : in std_logic; 12 -- FiberConnected : in std_logic; 13 -- GOL_RXN : in std_logic; 14 -- GOL_RXP : in std_logic; 15 -- GOL_TXN : out std_logic; 16 -- GOL_TXP : out std_logic; 17 -- LoopBack : in std_logic); 18 -- 19 -- EASE/HDL end ---------------------------------------------------------------- 20 21 architecture a0 of Fiber is 22 23 begin 24 Process (CSM_RXN, CSM_RXP, GOL_RXN, GOL_RXP, FiberConnected, LoopBack) 25 Begin 26 If FiberConnected = '1' Then 27 If LoopBack = '0' Then 28 GOL_TxP <= CSM_RxP; 29 GOL_TxN <= CSM_RxN; 30 Else 31 GOL_TxP <= GOL_RxP; 32 GOL_TxN <= GOL_RxN; 33 End If; 34 Else 35 GOL_TxP <= '1'; 36 GOL_TxN <= '0'; 37 End If; 38 End Process; 39 end architecture a0 ; -- of Fiber 40 41