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MROD_X_In

RocketSink

Documentation for architecture MROD_X_In/RocketSink/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RocketSink'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     OutputFileName :  String := "RocketSink.out");
   11  --   port(
   12  --     Clk  : in     std_logic;
   13  --     Data : in     std_logic_Vector(31 downto 0);
   14  --     WEN  : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of RocketSink is
   19  
   20  BEGIN
   21     Process (Clk, WEN)
   22        File OutpFile: ASCII_Text Open Write_Mode Is OutputFileName;
   23        Variable Hex_Str: String(1 To MAX_STRING_LEN);
   24     Begin   
   25  
   26        If Rising_Edge(Clk) And WEN = '1' Then
   27           fprint(OutpFile,"        %s\n",
   28              To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
   29           );
   30        End If;
   31  
   32     End Process;
   33  end architecture a0 ; -- of RocketSink
   34