Generated by EASE/HDL for peterj on Mon Jul 02 11:00:56 2007

Documentation for architecture MROD_X_In/Unused/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Unused'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr         : in     std_logic_Vector(21 downto 0);
   11  --     MS3_n       : in     std_logic;
   12  --     Reg3Fd      : out    std_logic_Vector(14 downto 0);
   13  --     SDRAM_A     : out    std_logic_Vector(12 downto 0);
   14  --     SDRAM_BA    : out    std_logic_Vector(1 downto 0);
   15  --     SDRAM_CAS_n : out    std_logic;
   16  --     SDRAM_CKE   : out    std_logic;
   17  --     SDRAM_CLK   : out    std_logic;
   18  --     SDRAM_CLKin : in     std_logic;
   19  --     SDRAM_CS_n  : out    std_logic;
   20  --     SDRAM_DQ    : inout  std_logic_Vector(31 downto 0);
   21  --     SDRAM_DQM   : out    std_logic_Vector(3 downto 0);
   22  --     SDRAM_RAS_n : out    std_logic;
   23  --     SDRAM_WE_n  : out    std_logic;
   24  --     Spare       : out    std_logic_Vector(4 downto 0);
   25  --     TestCon     : out    std_logic_Vector(15 downto 0));
   26  -- 
   27  -- EASE/HDL end ----------------------------------------------------------------
   28  
   29  architecture a0 of Unused is
   30  
   31  begin
   32     SDRAM_A <= (Others => '0');
   33     SDRAM_BA <= (Others => '0');
   34     SDRAM_CAS_n <= '1';
   35     SDRAM_CKE <= '0';
   36     SDRAM_CLK <= '0';
   37     SDRAM_CS_n <= '1';
   38     SDRAM_DQ <= (Others => '0');
   39     SDRAM_DQM <= (Others => '0');
   40     SDRAM_RAS_n <= '1';
   41     SDRAM_WE_n <= '1';
   42     Spare <= (Others => '0');
   43     TestCon <= (Others => '0');
   44     --TestCon <= Tst;
   45     
   46     -- Xilinx ISE software optimizes away unused inputs.
   47     -- There is no other alternative then to add dummy functionality
   48     -- to avoid MAP throwing away unused input pins
   49     -- See Xilinx "Case # 538535 preserve unused input pins"
   50     -- Thus, make it possible to readback these input pins in a dummy register
   51     Reg3Fd(0) <= MS3_n And Adr(0);
   52     Reg3Fd(1) <= SDRAM_CLKin;   
   53     Reg3Fd(2) <= '0';
   54     Reg3Fd(3) <= '0';
   55     Reg3Fd(11 downto 4) <= (Others => '0');
   56     Reg3Fd(14 downto 12) <= "000";
   57  
   58  end architecture a0 ; -- of Unused
   59  
   60