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MROD_X_In

TstGroup

Documentation for architecture MROD_X_In/TstGroup/rtl

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'rtl' of entity 'TstGroup'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Data         : in     std_logic_Vector(31 downto 0);
   11  --     Q            : out    std_logic_Vector(14 downto 0);
   12  --     RDA          : in     std_logic;
   13  --     RxClk        : in     std_logic;
   14  --     RxClkOut     : out    std_logic;
   15  --     RxLossOfSync : in     std_logic_Vector(1 downto 0);
   16  --     TDC_ParError : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture rtl of TstGroup is
   21  
   22  begin
   23     Q(14) <= RxLossOfSync(0);
   24     Q(13) <= TDC_ParError;
   25     Q(12) <= RDA;
   26     q(11 downto 0) <= Data(11 downto 0);
   27     RxClkOut <= RxClk;
   28  end architecture rtl ; -- of TstGroup
   29  
   30