Generated by
EASE/HDL
for
peterj
on Mon Jul 02 10:55:31 2007
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Index
MROD_X_Out
Documentation for entity MROD_X_Out/TTC_Interrupt
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u0:
WritePulse
: a0
Component: u1:
HoldFF
: a0
Component: u2:
AndG2
: a0
Component: u3:
MaskLogic
: a0
Component: u4:
RegEn1
: a0
Component: u5:
Inv1
: a0
Component: u6:
HoldFF
: a0
Component: u7:
AndG2
: a0
Component: u8:
MaskLogic
: a0
Component: u9:
RegEn1
: a0
Component: u10:
Inv1
: a0
Component: u14:
RegEn1
: a0
Component: u15:
Inv1
: a0
Component: u16:
AndG2
: a0
Component: u19:
Low1
: a0
Component: u11:
HoldFF
: a0
Component: u18:
AndG2
: a0
Component: u20:
MaskLogic
: a0
Component: u21:
RegEn1
: a0
Component: u22:
Inv1
: a0
Component: u23:
HoldFF
: a0
Component: u24:
AndG2
: a0
Component: u25:
MaskLogic
: a0
Component: u26:
RegEn1
: a0
Component: u27:
Inv1
: a0
Component: u12:
Gen_IRQ2
: rtl
Component: u28:
HoldFF
: a0
Component: u29:
AndG2
: a0
Component: u30:
MaskLogic
: a0
Component: u31:
RegEn1
: a0
Component: u32:
Inv1
: a0
Component: u33:
Inv1
: a0
Component: u13:
Low
: a0
Component: u34:
Low1
: a0
Component: u17:
Low
: a0
Component: u35:
Low
: a0
Component: u36:
Reg1
: a0
Component: u37:
Reg1
: a0
Component: u38:
Reg1
: a0
Component: u39:
Reg1
: a0
Component: u40:
Reg1
: a0
Component: u41:
Reg1
: a0
Component: u42:
Reg1
: a0
Component: u43:
Reg1
: a0