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MROD_X_Out

SR_FF

Documentation for architecture MROD_X_Out/SR_FF/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'SR_FF'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     Q     : out    std_logic;
   12  --     R     : in     std_logic;
   13  --     Rst_n : in     std_logic;
   14  --     S     : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of SR_FF is
   19  
   20  begin
   21     Process(Clk, Rst_n)
   22     Begin
   23        If Rst_n = '0' Then
   24           Q <= '0';
   25        ElsIf Rising_Edge(Clk) Then
   26  
   27           --Reset has preference over Set!
   28  
   29           If R = '1' Then
   30              Q <= '0';
   31           ElsIf S = '1' Then
   32              Q <= '1';
   33           End If;
   34        End If;
   35     End Process;
   36  end architecture a0 ; -- of SR_FF
   37