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ZBase

RegSC

Documentation for architecture ZBase/RegSC/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegSC'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     Clr   : in     std_logic;
   12  --     Q     : out    std_logic;
   13  --     Rst_n : in     std_logic;
   14  --     Set   : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of RegSC is
   19  
   20  begin
   21  
   22    pr0:
   23    process (Clk, Rst_n)
   24    begin
   25      if (Rst_n = '0') then
   26        Q <= '0';
   27      elsif (rising_edge(Clk)) then
   28        if (Set = '1') then
   29          Q <= '1';
   30        elsif (Clr = '1') then
   31          Q <= '0';
   32        end if;
   33      end if;
   34    end process;
   35  
   36  end architecture a0 ; -- of RegSC
   37  
   38