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MROD_X_In

IndexGen

Documentation for architecture MROD_X_In/IndexGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'IndexGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Index  : out    std_logic_Vector(17 downto 0);
   11  --     TDC_No : in     std_logic_Vector(4 downto 0));
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of IndexGen is
   16  BEGIN
   17     Process (TDC_No)
   18        Variable Number: Natural Range 31 downto 0;
   19     Begin
   20        Number := To_Integer(Unsigned(TDC_No));
   21        Index <= (Others => '0'); 
   22        If Number <= 17 Then
   23           Index(Number) <= '1';
   24        End If;
   25     End Process;
   26  end architecture a0 ; -- of IndexGen
   27