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MROD_X_Out

Documentation for entity MROD_X_Out/FPGA_Temp_Reg

Architectures

• Architecture: a0
  • Component: u0: WritePulse : a0
  • Component: u1: Inv1 : a0
  • Component: u2: RegEn1 : a0
  • Component: u3: RegEn1 : a0
  • Component: u4: RegEn1 : a0
  • Component: u5: Tri1 : a0
  • Component: u6: Buf1 : a0
  • Component: u7: Buf1 : a0