Back

Index

MGTR

FIFO8191wn

Documentation for architecture MGTR/FIFO8191wn/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'FIFO8191wn'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     AFull : out    std_logic;
   11  --     D     : in     std_logic_vector(31 downto 0);
   12  --     Empty : out    std_logic;
   13  --     NFull : out    std_logic;
   14  --     Q     : out    std_logic_vector(31 downto 0);
   15  --     RClk  : in     std_logic;
   16  --     RdReq : in     std_logic;
   17  --     Rst_n : in     std_logic;
   18  --     WClk  : in     std_logic;
   19  --     WrReq : in     std_logic);
   20  -- 
   21  -- EASE/HDL end ----------------------------------------------------------------
   22  
   23  architecture a0 of FIFO8191wn is
   24  
   25  -- This entity and architecture make a wrapper around the fifo8191w32n component.
   26  -- (The component was generated with Xilinx Core Generator.)
   27  
   28    component fifo8191w32n
   29      port (
   30        din: IN std_logic_vector(31 downto 0);
   31        wr_en: IN std_logic;
   32        wr_clk: IN std_logic;
   33        rd_en: IN std_logic;
   34        rd_clk: IN std_logic;
   35        rst: IN std_logic;
   36        dout: OUT std_logic_vector(31 downto 0);
   37        full: OUT std_logic;
   38        empty: OUT std_logic;
   39        almost_full: OUT std_logic;
   40        almost_empty: OUT std_logic;
   41        wr_data_count: OUT std_logic_vector(12 downto 0)
   42      );
   43    end component;
   44  
   45    signal InternReset: std_logic;
   46    signal InternFull:  std_logic;
   47    signal InternCount: std_logic_vector(12 downto 0);
   48  
   49  begin
   50  
   51    InternReset <= not Rst_n;
   52    NFull <= '1' when (InternFull = '1' or InternCount(12 downto 3) = "1111111111") else '0';
   53    -- Nearly full when 7 or less words can be written.
   54  
   55    uc1: fifo8191w32n
   56    port map (
   57      din => D,
   58      wr_en => WrReq,
   59      wr_clk => WClk,
   60      rd_en => RdReq,
   61      rd_clk => RClk,
   62      rst => InternReset,
   63      dout => Q,
   64      full => InternFull,
   65      empty => Empty,
   66      almost_full => AFull,
   67      almost_empty => open,
   68      wr_data_count => InternCount
   69      );
   70  
   71  end architecture a0 ; -- of FIFO8191wn
   72