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MROD_X_Out

CombReg2d

Documentation for architecture MROD_X_Out/CombReg2d/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'CombReg2d'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Bit10  : in     std_logic;
   11  --     Bit11  : in     std_logic;
   12  --     Bit12  : in     std_logic;
   13  --     Bit13  : in     std_logic;
   14  --     Bit14  : in     std_logic;
   15  --     Bit15  : in     std_logic;
   16  --     Bit3_0 : in     std_logic_vector(3 downto 0);
   17  --     Bit4   : in     std_logic;
   18  --     Bit5   : in     std_logic;
   19  --     Bit6   : in     std_logic;
   20  --     Bit7   : in     std_logic;
   21  --     Bit8   : in     std_logic;
   22  --     Bit9   : in     std_logic;
   23  --     Reg2d  : out    std_logic_vector(31 downto 0));
   24  -- 
   25  -- EASE/HDL end ----------------------------------------------------------------
   26  
   27  architecture a0 of CombReg2d is
   28  
   29  begin
   30     Reg2d(3 downto 0) <= Bit3_0;
   31     Reg2d(4) <= Bit4;
   32     Reg2d(5) <= Bit5;
   33     Reg2d(6) <= Bit6;
   34     Reg2d(7) <= Bit7;
   35     Reg2d(8) <= Bit8;
   36     Reg2d(9) <= Bit9;
   37     Reg2d(10) <= Bit10;
   38     Reg2d(11) <= Bit11;
   39     Reg2d(12) <= Bit12;
   40     Reg2d(13) <= Bit13;
   41     Reg2d(14) <= Bit14;
   42     Reg2d(15) <= Bit15;
   43     Reg2d(31 downto 16) <= (Others => '0');
   44  end architecture a0 ; -- of CombReg2d
   45  
   46