Generated by EASE/HDL for peterj on Mon Jul 02 10:55:25 2007

Documentation for architecture MROD_X_Out/AdrMux/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'AdrMux.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'AdrMux' :
    5  -- 
    6  --   generic(
    7  --     n :  positive := 8 );
    8  --   port(
    9  --     A   : in     std_logic_vector(n-1 downto 0);
   10  --     B   : in     std_logic_vector(n-1 downto 0);
   11  --     O   : out    std_logic_vector(n-1 downto 0);
   12  --     Sel : in     std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of AdrMux is
   17  
   18  BEGIN
   19     Process (A, B, Sel)
   20     Begin
   21        If Sel = '1' Then
   22           O <= B;
   23        Else
   24           O <= A;
   25        End If;
   26     End Process;
   27  end architecture a0 ; -- of AdrMux
   28