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MROD_X_Out

Dec_USER_AM10

Documentation for architecture MROD_X_Out/Dec_USER_AM10/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Dec_USER_AM10'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr          : in     std_logic_vector(31 downto 0);
   11  --     BAR          : in     std_logic_vector(7 downto 0);
   12  --     Clk          : in     std_logic;
   13  --     Cs_USER_AM10 : out    std_logic;
   14  --     DECODE       : in     std_logic;
   15  --     Rst_n        : in     std_logic;
   16  --     USER_AM10    : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of Dec_USER_AM10 is
   21     Signal InternalDecode: Boolean;
   22  BEGIN
   23     --VME Address lines A[23..19] are compared against the BAR to gain a unique address
   24     --within the VME-crate.
   25  
   26     InternalDecode <= (USER_AM10 = '1' And (BAR(7 Downto 3) = Adr(23 Downto 19)));
   27  
   28     Process (Clk, Rst_n)
   29     Begin
   30        If Rst_n = '0' Then
   31           Cs_USER_AM10 <= '0';
   32        ElsIf Rising_Edge(Clk) Then
   33           --the Chip Select signal is continuously updated but as soon as the
   34           --DECODE signal arrives the result is holded for the duration of DECODE
   35           --Note this covers the complete Address Phase (AS_n)
   36           If DECODE = '0' Then
   37              If InternalDecode = True Then
   38                 Cs_USER_AM10 <= '1';
   39              Else
   40                 Cs_USER_AM10 <= '0';
   41              End If;
   42           End If;
   43        End If;
   44     End Process;
   45  end architecture a0 ; -- of Dec_USER_AM10
   46