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MROD_X_Out

ShuffleEV_BC_ID_Bits

Documentation for architecture MROD_X_Out/ShuffleEV_BC_ID_Bits/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'ShuffleEV_BC_ID_Bits'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     EV_BC_ID       : in     std_logic_vector(35 downto 0);
   11  --     Extended_EV_ID : in     std_logic_vector(7 downto 0);
   12  --     Q              : out    std_logic_vector(43 downto 0));
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of ShuffleEV_BC_ID_Bits is
   17  
   18  begin
   19     Q(43 downto 32) <= EV_BC_ID(35 downto 24);
   20     Q(31 downto 24) <= Extended_EV_ID;
   21     Q(23 downto 0) <= EV_BC_ID(23 downto 0);
   22  end architecture a0 ; -- of ShuffleEV_BC_ID_Bits
   23  
   24