Generated by
EASE/HDL
for
peterj
on Mon Jul 02 11:00:50 2007
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Index
MGTR
Documentation for entity MGTR/STBuffer
Contents
Side Data
Generated HDL
Architectures
Architecture:
a0
Component: u5:
And1Inv
: a0
Component: u6:
And1Inv
: a0
Component: u8:
RegEV
: a0
Component: u9:
RegD
: a0
Component: u2:
And1Inv
: a0
Component: u3:
RegD
: a0
Component: u10:
RegDV
: a0
Component: u11:
RegD
: a0
Component: u12:
RegDV
: a0
Component: u13:
RegD
: a0
Component: u4:
FIFO511wn
: a0
Component: u7:
FIFO8191wn
: a0
Component: u1:
FIFO511wn
: a0