Documentation for architecture MROD_X_In/FIFO_GOLA/a0
VHDL Contents
1 architecture a0 of FIFO_GOLA is
23 component fifo_gola_32x511
24 port (
25 din: IN std_logic_VECTOR(31 downto 0);
26 wr_en: IN std_logic;
27 wr_clk: IN std_logic;
28 rd_en: IN std_logic;
29 rd_clk: IN std_logic;
30 ainit: IN std_logic;
31 dout: OUT std_logic_VECTOR(31 downto 0);
32 full: OUT std_logic;
33 empty: OUT std_logic);
34 end component;
35 signal InternReset: Std_Logic;
36 begin
37
38 InternReset <= Not Rst_n;
39
40 U0: fifo_gola_32x511
41 port map (
42 din => D,
43 wr_en => WrReq,
44 wr_clk => Rx_Clk,
45 rd_en => RdReq,
46 rd_clk => Clk,
47 ainit => InternReset,
48 dout => Q,
49 full => Full,
50 empty => Empty);
51 end architecture a0 ;