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MROD_X_In

MGT_GOL_Container

Documentation for architecture MROD_X_In/MGT_GOL_Container/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'MGT_GOL_Container'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     BRefClk        : in     std_logic;
   11  --     PowerDown      : in     std_logic;
   12  --     RXUsrClk       : in     std_logic;
   13  --     RXUsrClk2      : in     std_logic;
   14  --     TXData         : in     std_logic_Vector(31 downto 0);
   15  --     TXN            : out    std_logic;
   16  --     TXP            : out    std_logic;
   17  --     TXUsrClk       : in     std_logic;
   18  --     TXUsrClk2      : in     std_logic;
   19  --     TxBuffErr      : out    std_logic;
   20  --     TxCharDispMode : in     std_logic_Vector(3 downto 0);
   21  --     TxCharDispVal  : in     std_logic_Vector(3 downto 0);
   22  --     TxCharIsK      : in     std_logic_Vector(3 downto 0);
   23  --     TxInhibbit     : in     std_logic;
   24  --     TxKErr         : out    std_logic_Vector(3 downto 0);
   25  --     TxPolarity     : in     std_logic;
   26  --     TxReset        : in     std_logic;
   27  --     TxRunDisp      : out    std_logic_Vector(3 downto 0));
   28  -- 
   29  -- EASE/HDL end ----------------------------------------------------------------
   30  
   31  architecture a0 of MGT_GOL_Container is
   32      
   33      Component MGT_GOL
   34          port (
   35            BREFCLK           : in    std_logic; 
   36            ENMCOMMAALIGN_IN  : in    std_logic; 
   37            ENPCOMMAALIGN_IN  : in    std_logic; 
   38            LOOPBACK_IN       : in    std_logic_vector (1 downto 0); 
   39            POWERDOWN         : in    std_logic; 
   40            RXN_IN            : in    std_logic; 
   41            RXPOLARITY_IN     : in    std_logic; 
   42            RXP_IN            : in    std_logic; 
   43            RXRESET_IN        : in    std_logic; 
   44            RXUSRCLK          : in    std_logic; 
   45            RXUSRCLK2         : in    std_logic; 
   46            TXCHARDISPMODE    : in    std_logic_vector (3 downto 0); 
   47            TXCHARDISPVAL     : in    std_logic_vector (3 downto 0); 
   48            TXCHARISK         : in    std_logic_vector (3 downto 0); 
   49            TXDATA            : in    std_logic_vector (31 downto 0); 
   50            TXINHIBIT         : in    std_logic; 
   51            TXPOLARITY        : in    std_logic; 
   52            TXRESET           : in    std_logic; 
   53            TXUSRCLK          : in    std_logic; 
   54            TXUSRCLK2         : in    std_logic; 
   55            RXBUFSTATUS_OUT   : out   std_logic_vector (1 downto 0); 
   56            RXCHARISCOMMA_OUT : out   std_logic_vector (3 downto 0); 
   57            RXCHARISK_OUT     : out   std_logic_vector (3 downto 0); 
   58            RXCLKCORCNT_OUT   : out   std_logic_vector (2 downto 0); 
   59            RXCOMMADET_OUT    : out   std_logic; 
   60            RXDATA_OUT        : out   std_logic_vector (31 downto 0); 
   61            RXDISPERR_OUT     : out   std_logic_vector (3 downto 0); 
   62            RXLOSSOFSYNC_OUT  : out   std_logic_vector (1 downto 0); 
   63            RXNOTINTABLE_OUT  : out   std_logic_vector (3 downto 0); 
   64            RXREALIGN_OUT     : out   std_logic; 
   65            RXRECCLK_OUT      : out   std_logic; 
   66            RXRUNDISP_OUT     : out   std_logic_vector (3 downto 0); 
   67            TXBUFERR          : out   std_logic; 
   68            TXKERR            : out   std_logic_vector (3 downto 0); 
   69            TXN               : out   std_logic; 
   70            TXP               : out   std_logic; 
   71            TXRUNDISP         : out   std_logic_vector (3 downto 0));
   72      End Component;
   73  
   74     signal GND : std_logic_vector (3 downto 0);
   75     signal GND1 : std_logic;
   76     signal GND2 : std_logic_vector (1 downto 0);
   77  
   78      begin
   79      U0: MGT_GOL
   80           port map (
   81            BREFCLK => BRefClk,
   82            ENMCOMMAALIGN_IN => GND1,
   83            ENPCOMMAALIGN_IN => GND1,
   84            LOOPBACK_IN => GND2(1 downto 0),
   85            POWERDOWN => PowerDown,
   86            RXN_IN => GND1,
   87            RXPOLARITY_IN => GND1,
   88            RXP_IN => GND1,
   89            RXRESET_IN => GND1,
   90            RXUSRCLK => RXUsrClk,
   91            RXUSRCLK2 => RXUsrClk2,
   92            TXCHARDISPMODE => TXCharDispMode,
   93            TXCHARDISPVAL => TXCharDispVal,
   94            TXCHARISK => TXCharIsK,
   95            TXDATA => TXData,
   96            TXINHIBIT => TXInhibbit,
   97            TXPOLARITY => TXPolarity,
   98            TXRESET => TXReset,
   99            TXUSRCLK => TXUsrClk,
  100            TXUSRCLK2 => TXUsrClk2,
  101            RXBUFSTATUS_OUT => open,
  102            RXCHARISCOMMA_OUT => open,
  103            RXCHARISK_OUT => open,
  104            RXCLKCORCNT_OUT => open,
  105            RXCOMMADET_OUT => open,
  106            RXDATA_OUT => open,
  107            RXDISPERR_OUT => open,
  108            RXLOSSOFSYNC_OUT => open,
  109            RXNOTINTABLE_OUT => open,
  110            RXREALIGN_OUT => open,
  111            RXRECCLK_OUT => open,
  112            RXRUNDISP_OUT => open,
  113            TXBUFERR => TXBuffErr,
  114            TXKERR => TXKErr,
  115            TXN => TXN,
  116            TXP => TXP,
  117            TXRUNDISP => TXRunDisp);
  118            
  119      GND <= "0000";
  120      GND1 <= '0';
  121      GND2 <= "00";
  122  
  123  end architecture a0 ; -- of MGT_GOL_Container
  124  
  125