High REsolution Large Area X-ray Detector
Miniaturization of electronics has caused the digital revolution. The present-day circuit-design and semiconductor processing technologies have enabled us to completely change the way in which X-rays are detected and processed in commercial X-ray diffraction (XRD) and X-ray fluorescence (XRF) equipment. Here we propose to add even more functionality to such equipment, by means of tiling together several single photon-counting pixel-readout circuit on one single semi conducting sensor chip. Many new applications can be targeted, in materials research as well as in life-sciences, e.g. proteomics and pharmacological research, if such a large-area detector system can be designed and built.
Artistic visualization of the Relaxd detector frame with edge-less detector modules (left/top)Visualization of the Relaxd detector frame with prototype wire-bonded modules using high speed readout (right/bottom)
Cross section of the thru-via interconnections and detector fanout
Principle of through-silicon via interconnect and pitch adaptation between sensor pixels:
We want to reduce Medipix2 insensitive area by removing the wire bond connections. For this, we will etch high-aspect ration holes through the wire bond pads on the chip. The diameter and the depth of these holes will be about 50µm. The holes will be filled with an insulator (BCB, Polyimide) and then small holes will be etched in the insulator and filled with metal (Copper, Copper alloy). The open metal contacts will be connected to solder bumps (~100µm diameter).
The sensor will be a planar, active edge sensor, eliminating the need for guardring structures and allowing sensitivity up to 10µm from the edges. For this purpose, we will increase the sensor dimension to cover the full area of the readout chips. This will demand a considerably larger pitch adaptation of 12%.
Block schematics of the Relaxd readout module
Chip-parallel readout for the Quad microsystem:
The clock and data signals are 200 MHz and are multiplexed/demultiplexed into one high-bandwith, clock encoded in the data, signal of around 1 Gbit/s. In this architecture, chips are read out in parallel and the total readout time for an 4-chip assembly is about 5 ms.
Below you can see pictures of the prototype device. The readout speed achieved with standard ethernet cat5 cable is 3 Gbit/s to special Motherboard using our own communication protocol. Direct connection to laptop or table PC using standard 1-Gigabit Ethernet is also possible with this reduced speed.
Prototype of the Relaxd high-speed readout module connected to the quad chipboard (wire-bonded version)