The MROD (MDT Read Out Driver) has to build event fragments from the data of 6 MDT muon chambers.
On each muon chamber the data of at maximum 18 TDCs, with 24
channels
each, will be multiplexed by the Chamber Service Module (CSM)
on one Gigabit Optical Link (GOL) using the GOL chip, so the MROD has 6 inputs
for these links and one source S-link interface for the Read-Out Link
(ROL) to be connected to a ROB (Read-Out Buffer) . The MROD-1 design consists of a 9
U VME board with 6 inputs, each with a connector for a S-link
destination card, one source S-link interface, a VME64x interface
and an interface to the TTC system. The design makes use of SHARC-II
processors
(ADSP-21160) in conjunction with Altera FPGAs. Links based on the GOL
chip as well as standard S-links can be connected to the inputs using
appropriate daughter boards.
The MROD-X design builds upon the MROD-1 design. In it the Altera
FPGAs are replaced by Xilinx FPGAs, which are connected with "RocketIO"
links. Although the MROD-X can be used in an MROD-1 compatible mode,
during normal operation event data will be transported via the
"RocketIO"
links and fragment building is done in the FPGA connecting to the
output S-link, while the SHARCs take care of control and monitoring.
The MROD-X occupies a single VME slot and has 6 or 8 (prototypes only) inputs for GOL
links.
There are no daughter boards, except the obligatory S-link source card
for the Read-Out Link. Six fully-functional prototype modules are
available, a picture of the assembled PCB is shown below. The
Production Readiness Review has taken place on 2 November 2005, the
production of about 255 modules with 6 inputs is under way, a pre-series of 15 modules is fully functional.
Documents for Production Readiness Review of 2 November 2005 (Agenda review meeting)
Slides
for Intermediate Design Review of 12
November 2003 (Agenda review
meeting)
Links to documents
Links
to relevant web pages