Date: Mon, 14 Jan 2002 11:51:06 +0100 (MET)
From: Krzysztof Korcyl <korcyl@chall.ifj.edu.pl>
To: atlas-tdaq-model@cern.ch
Subject: UML diagrams of ethernet+switch models

Dear Modelers,

At our last modeling meeting (Nikhef, Amsterdam) I declared that within a
month some preliminary UML diagrams of the parameterized model of switch
should be available.

Well..., it is now more than a month, and they are still very preliminary,
but at least they exist!!!

You can have a look into

http://chall.ifj.edu.pl/~korcyl/UML

In that directory there are two class diagrams: ethernetClass.ps and
paramSwitchTopViewClass.ps. The first shows classes used to model the
Ethernet standard, and the latter the top view organization of classes
forming the parameterized model of a switch.

In that directory there are also 4 postscript files with sequence diagrams
for 4 main events driving the switch modeling:

1. packet arrival: packetArrivalSequence.ps

2. moment in time, when switch recognizes packet, defines it's internal
   routing (destination module/port) and is ready to start switching if
   there are enough resources: routingDecidedSequence.ps

3. moment in time when intermodule transfer completes, and some resources
   can be allocated for waiting frames: interTransferCompletedSequence.ps

4. moment in time when packet (frame) finally leaves the switch (output
   port is ready to start another transfer): frameLeftSequence.ps

If you have comments/suggestions/questions, please contact me. We can also
discuss them briefly during tomorrow's videoconference.

cheers,

Kris.


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