Jos Vermeulen, June 12, 1998

Present :

A. Amadon, Saclay
R. Blair, ANL
P. Clarke, UCL
R. Cranfield, UCL
G. Crone, UCL
W. Li, RHUL
J. Vermeulen, NIKHEF
Q. Zu, RHUL

The different tasks of the workplan presented in the April coordination meeting
provided themes for the agenda . The five tasks were :

Modelling-1-PaperModelUpdate
Modelling-2-FullGenericModel
Modelling-3-GenericTestSystemModels
Modelling-4-TechnologyModels
Modelling-5-FullModel

I Update of the paper model

In the ATLAS week from June 8 to June 12 new trigger menus will be presented by Dick Hubbard and Simon George. The menus to use for modelling have to be chosen. It is also anticipated that new numbers will be available with respect to number of ROBs, data sizes etc. .

A. Amadon produced new paper model results for architecture C, based on new trigger menus from Dick Hubbard and also modifications in parameters defined in DAQ note 70. He modified and used the Excel spreadsheet of JV, but removed parts not required for producing these results. AA will communicate the changes made to JV, so that JV can update the full version of the spreadsheet.

RHUL will not longer be active in the field of paper modelling. Simon George has recently produced a (hopefully) final version of the draft DAQ note on the results, which still has to be checked by JV.

II. Full generic model

P. Clarke has now a clear idea on the implementation of the sequential menus, also based on input from the reference testbed group. Implementation is for him the highest-priority task to be completed, where he will be assisted by R. Cranfield and G. Crone. K. Korcyl is still to do the sequential processing itself, but had to devote his time until the time of the meeting to other projects.

A. Amadon studied the tasks to be performed by the "model C processors" and by the SFIs and hopes to complete the implementation by August 1.

R. Blair has studied various algorithms for assigning the global processors, but found that there is not much difference in the latencies observed and does not have yet an explanation for this behaviour. Severla suggestions were made on possible approaches to investigate this. He plans to update the supervisor model.

JV presented an overview of the status of Simdaq-C++ as per June 1. An up to date version (version 3.1.a) for the various platforms is available via the web. He also mentioned the following list of items to be implemented :

1. handshaking on ports (needed for bus objects and DS-link demonstrator)
2. subdivision of messages in packets by output ports and assmebly of packets into messages by input ports
3. finite buffer sizes
4. bus object (e.g. for modelling PCI bus)
5. broadcasting in switch objects
6. XON-XOFF handshaking (this is different from 1, where the handshaking is done for each message of packet)

JV will try to make progress with implementing these items, for the bus objects using input from Peter Clarke and base the implementation of the finite buffer sizes on the ideas of Nick Ellis.

III. Generic models of test setups

JV explained that he had not been able to complete the generic model of the DS-link demonstrator due to the necessity to modify the model for the FEX processor, which requires handshaking on the input port on a per message basis. He will continue working on this subject.

R. Blair will take care of generic modelling of ATM-based test set-ups.

There was some discussion on the desirability of this type of modelling, in particular for the DS-link based demo set-up, as it is not clear what one can learn from modelling. JV noted that one may get ideas about models to be included in Simdaq-C++ and also that reproduction of the various measurement results by a single computer model is unlikely with a model containing inconsistencies.

IV. Technology models

Work is done on SCI in Ptolemy in Manchester. The desirability of detailed simulation of SCI in the framework of Simdaq-C++ depends on the interest in applying SCI in the trigger/DAQ system, which is perceived to be smaller than it was in the past.

A. Amadon will include suitably modified C++ code simulating ATM developed previously at Saclay in Simdaq-C++.

K. Korcyl will take care of implementing a model for Gigabit Ethernet in Simdaq-C++.

R. Blair looks after modelling of the supervisor.

P. Clarke, RHUL and G. Crone will study a ROBComplex consisting of several ROBIns sharing a PCI bus and with a gigabit Ethernet port using Ptolemy.

NBI is known to have modelled the DAQ-1 ROC crate and to work on the event builder. The convenors will approach J-R Hansen and/or B. Rensch to discuss coordination of the activities.

V. Full models

It is too early to do detailed planning for this task. The task description has been changed to reflect the fact that it represents a refinement in previous work rather than a separate task.

VI. Conclusion

The different tasks in the workplan and how to update it have been discussed, a new workplan is to be produced.

The convenors will set up a framework for a working document. This should evolve during the project period and finally contain the output of the project in the form of descriptions of models, methods, software and of results.

The next meeting is not necessarily directly after the planned ROB meeting at Saclay in the week from 5 - 9 October. Peter Clarke will investigate the possibilities of video conferencing, in particular in view of reducing the amount of travelling of R. Blair. It is foreseen that the Chamonix workshop, which R. Blair intends to visit, will provide in any case the opportunity for direct contacts